View LTC6252_7788496.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LTC6252/ltc6253/ltc6254 1 625234fc typical application description 720mhz, 3.5ma power efficient rail-to-rail i/o op amps the ltc ? 6252/ltc6253/ltc6254 are single/dual/quad low power, high speed unity gain stable rail-to-rail input/output operational amplifiers. on only 3.5ma of supply current they feature a 720mhz gain-bandwidth product, 280v/s slew rate and a low 2.75nv/ hz of input-referred noise. the combination of high bandwidth, high slew rate, low power consumption and low broadband noise makes the LTC6252 family unique among rail-to-rail input/output op amps with similar supply currents. they are ideal for lower supply voltage high speed signal conditioning systems. the LTC6252 family maintains high efficiency performance from supply voltage levels of 2.5v to 5.25v and is fully specified at supplies of 2.7v and 5.0v. for applications that require power-down, the LTC6252 and the ltc6253 in ms10 offer a shutdown pin which disables the amplifier and reduces current consumption to 42a. the LTC6252 family can be used as a plug-in replacement for many commercially available op amps to reduce power or to improve input/output range and performance. l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. features applications n gain bandwidth product: 720mhz n C3db frequency (a v = 1): 400mhz n low quiescent current: 3.5ma max n high slew rate: 280v/s n input common mode range includes both rails n output swings rail-to-rail n low broadband voltage noise: 2.75nv/ hz n power-down mode: 42a n fast output recovery n supply voltage range: 2.5v to 5.25v n input offset voltage: 350v max n large output current: 90ma n cmrr: 105db n open loop gain: 60v/mv n operating temperature range: C40c to 125c n single in 6-pin tsot-23 n dual in ms8, 2mm 2mm dfn, 8-pin ts0t-23, ms10 n quad in ms16 n low voltage, high frequency signal processing n driving a/d converters n rail-to-rail buffer amplifiers n active filters n battery powered equipment 5v single-supply 16-bit adc driver ltc6253 driving ltc2393-16 16-bit adc 5v single-supply performance 5v 0.1f 10f 5v 5v ~2.08v 0.1f 10f ser/ par byteswap ob/2c cs rd busy parallel or serial interface ognd 625234 ta01 in ? in + 3900pf 249 100 249 100 v in 27.4mv to (3.5v + 27.4mv) gnd reset cnvst pd sample clock refout refin avp dvp ltc2393-16 ovp 1.8v to 5v 16 bit vcm 1f 10f 2.5k 2.5k 143 845 4.7f ? + ? ltc6253 5v ? + ? ltc6253 frequency (khz) 0 amplitude (dbfs) 0 ?80 ?20 ?40 ?60 ?100 ?120 ?140 ?160 200 400 100 300 624678 ta01b 500 f s = 1msps f1 = 20.111khz f1 amplitude = ?1.032dbfs snr = 93.28db thd = ?100.50db sinad = 92.53db sfdr = 104.7db f2 = ?106.39dbc f3 = ?104.70dbc f4 = ?114.13dbc f5 = ?105.48dbc
LTC6252/ltc6253/ltc6254 2 625234fc absolute maximum ratings pin configuration order information lead free finish tape and reel part marking* package description specified temperature range LTC6252cs6#trmpbf LTC6252cs6#trpbf ltfrw 6-lead plastic tsot-23 0c to 70c LTC6252is6#trmpbf LTC6252is6#trpbf ltfrw 6-lead plastic tsot-23 C40c to 85c LTC6252hs6#trmpbf LTC6252hs6#trpbf ltfrw 6-lead plastic tsot-23 C40c to 125c ltc6253cdc#trmpbf ltc6253cdc#trpbf lfrz 8-lead (2mm 2mm) plastic dfn 0c to 70c ltc6253idc#trmpbf ltc6253idc#trpbf lfrz 8-lead (2mm 2mm) plastic dfn C40c to 85c ltc6253cms8#pbf ltc6253cms8#trpbf ltfrx 8-lead plastic msop 0c to 70c ltc6253ims8#pbf ltc6253ims8#trpbf ltfrx 8-lead plastic msop C40c to 85c ltc6253hms8#pbf ltc6253hms8#trpbf ltfrx 8-lead plastic msop C40c to 125c ltc6253cts8#trmpbf ltc6253cts8#trpbf ltfry 8-lead plastic tsot-23 0c to 70c ltc6253its8#trmpbf ltc6253its8#trpbf ltfry 8-lead plastic tsot-23 C40c to 85c ltc6253hts8#trmpbf ltc6253hts8#trpbf ltfry 8-lead plastic tsot-23 C40c to 125c total supply voltage (v + to v C ) ................................ 5.5v input current (+in, Cin, shdn ) (note 2) .............. 10ma output current (note 3) ..................................... 100ma operating temperature range (note 4) .. C40c to 125c specified temperature range (note 5) .. C40c to 125c storage temperature range .................. C65c to 150c junction temperature ........................................... 150c lead temperature (soldering, 10 sec) msop, tsot packages only ............................. 300c out 1 v ? 2 +in 3 6 v + 5 shdn 4 ?in top view s6 package 6-lead plastic tsot-23 + ? t jmax = 150c, q ja = 192c/w (note 9) top view out a ?in a +in a v ? v + out b ?in b +in b dc package 8-lead (2mm 2mm) plastic dfn 9 4 1 2 3 6 5 7 8 + ? + ? t jmax = 125c, q ja = 102c/w (note 9) exposed pad (pin 9) is v C , must be soldered to pcb 1 2 3 4 out a ?in a +in a v ? 8 7 6 5 v + out b ?in b +in b top view ms8 package 8-lead plastic msop + ? + ? t jmax = 150c, q ja = 163c/w (note 9) 1 2 3 4 5 out a ?in a +in a v ? shdna 10 9 8 7 6 v + out b ?in b +in b shdnb top view ms package 10-lead plastic msop + ? + ? t jmax = 150c, q ja = 160c/w (note 9) out a 1 ?in a 2 +in a 3 v ? 4 8 v + 7 out b 6 ?in b 5 +in b top view ts8 package 8-lead plastic tsot-23 + ? + ? t jmax = 150c, q ja = 195c/w (note 9) 1 2 3 4 5 6 7 8 out a ?in a +in a v + +in b ?in b out b 16 15 14 13 12 11 10 9 out d ?in d +in d v ? +in c ?in c out c top view ms package 16-lead plastic msop + ? + ? + ? + ? t jmax = 150c, q ja = 125c/w (note 9) (note 1)
LTC6252/ltc6253/ltc6254 3 625234fc (v s = 5v) the l denotes the specifications which apply across the specified temperature range, otherwise specifications are at t a = 25c. for each amplifier v s = 5v, 0v; v shdn = 2v; v cm = v out = 2.5v, unless otherwise noted. order information lead free finish tape and reel part marking* package description specified temperature range ltc6253cms#pbf ltc6253cms#trpbf ltfsb 10-lead plastic msop 0c to 70c ltc6253ims#pbf ltc6253ims#trpbf ltfsb 10-lead plastic msop C40c to 85c ltc6254cms#pbf ltc6254cms#trpbf 6254 16-lead plastic msop 0c to 70c ltc6254ims#pbf ltc6254ims#trpbf 6254 16-lead plastic msop C40c to 85c ltc6254hms#pbf ltc6254hms#trpbf 6254 16-lead plastic msop C40c to 125c trm = 500 pieces. *temperature grades are identified by a label on the shipping container. consult ltc marketing for parts specified with wider operating temperature ranges. consult ltc marketing for information on lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ electrical characteristics symbol parameter conditions min typ max units v os input offset voltage v cm = half supply l C350 C1000 50 350 1000 v v v cm = v + C 0.5v, npn mode l C2.2 C3.3 0.1 2.2 C3.3 mv mv dv os input offset voltage match (channel-to-channel) (note 8) v cm = half supply l C350 C550 50 350 550 v v v cm = v + C 0.5v, npn mode l C2.75 C4 0.1 2.75 4 mv mv v os t c input offset voltage drift l C3.5 v/c i b input bias current (note 7) v cm = half supply l C0.75 C1.15 C0.1 0.75 1.15 a a v cm = v + C 0.5v, npn mode l 0.8 0.4 1.4 3.0 5.0 a a i os input offset current v cm = half supply l C0.5 C0.6 C0.03 0.5 0.6 a a v cm = v + C 0.5v, npn mode l C0.5 C0.6 C0.03 0.5 0.6 a a e n input noise voltage density f = 1mhz 2.75 nv/ hz input 1/f noise voltage f = 0.1hz to 10hz 2 v p-p i n input noise current density f = 1mhz 4 pa/hz c in input capacitance differential mode common mode 2.5 0.8 pf pf r in input resistance differential mode common mode 7.2 3 k? m? a vol large signal voltage gain r l = 1k to half supply (note 10) l 35 16 60 v/mv v/mv r l = 100? to half supply (note 10) l 5 2.4 13 v/mv v/mv cmrr common mode rejection ratio v cm = 0v to 3.5v l 85 82 105 db db
LTC6252/ltc6253/ltc6254 4 625234fc electrical characteristics symbol parameter conditions min typ max units v cmr input common mode range l 0 v s v psrr power supply rejection ratio v s = 2.5v to 5.25v v cm = 1v l 66.5 62 70 db db supply voltage range (note 6) l 2.5 5.25 v v ol output swing low (v out C v C ) no load l 25 40 65 mv mv i sink = 5ma l 60 90 120 mv mv i sink = 25ma l 150 200 320 mv mv v oh output swing high (v + C v out ) no load l 65 100 120 mv mv i source = 5ma l 115 170 210 mv mv i source = 25ma l 270 330 450 mv mv i sc output short-circuit current sourcing l C90 C40 C32 ma ma sinking l 60 40 100 ma ma i s supply current per amplifier v cm = half supply l 3.3 3.5 4.8 ma ma v cm = v + C 0.5v l 4.25 4.85 5.9 ma ma i sd disable supply current v shdn = 0.8v l 42 55 75 a a i shdnl shdn pin current low v shdn = 0.8v l C3 C4 C1.6 0 0 a a i shdnh shdn pin current high v shdn = 2v l C300 C600 35 300 600 na na v l shdn pin input voltage low l 0.8 v v h shdn pin input voltage high l 2 v i osd output leakage current in shutdown v shdn = 0.8v, output shorted to either supply 100 na t on turn-on time v shdn = 0.8v to 2v 3.5 s t off turn-off time v shdn = 2v to 0.8v 2 s bw C3db closed loop bandwidth a v = 1, r l = 1k to half supply 400 mhz gbw gain-bandwidth product f = 4mhz, r l = 1k to half supply l 450 320 720 mhz mhz t s , 0.1% settling time to 0.1% a v = 1, v o = 2v step r l = 1k 36 ns sr slew rate a v = C1, 4v step (note 11) 280 v/s fpbw full power bandwidth v out = 4v p-p (note 13) 9.5 mhz (v s = 5v) the l denotes the specifications which apply across the specified temperature range, otherwise specifications are at t a = 25c. for each amplifier v s = 5v, 0v; v shdn = 2v; v cm = v out = 2.5v, unless otherwise noted.
LTC6252/ltc6253/ltc6254 5 625234fc symbol parameter conditions min typ max units hd2/hd3 harmonic distortion r l = 1k to half supply f c = 100khz, v o = 2v p-p f c = 1mhz, v o = 2v p-p f c = 2.5mhz, v o = 2v p-p f c = 4mhz, v o = 2v p-p 99/109 97/104 83/82 77/71 dbc dbc dbc dbc r l = 100? to half supply f c = 100khz, v o = 2v p-p f c = 1mhz, v o = 2v p-p f c = 2.5mhz, v o = 2v p-p f c = 4mhz, v o = 2v p-p 97/90 95/70 87/65 78/59 dbc dbc dbc dbc dg differential gain (note 14) a v = 2, r l = 150, v s = 2.5v a v = 1, r l = 1k, v s = 2.5v 0.1 0.02 % % dq differential phase (note 14) a v = 2, r l = 150, v s = 2.5v a v = 1, r l = 1k, v s = 2.5v 0.25 0.05 deg deg crosstalk a v = C1, r l = 1k to half supply, v out = 2v p-p , f = 2.5mhz C96 db electrical characteristics (v s = 5v) the l denotes the specifications which apply across the specified temperature range, otherwise specifications are at t a = 25c. for each amplifier v s = 5v, 0v; v shdn = 2v; v cm = v out = 2.5v, unless otherwise noted. electrical characteristics (v s = 2.7v) the l denotes the specifications which apply across the specified temperature range, otherwise specifications are at t a = 25c. for each amplifier v s = 2.7v, 0v; v shdn = 2v; v cm = v out = 1.35v, unless otherwise noted. symbol parameter conditions min typ max units v os input offset voltage v cm = half supply l 0 C300 700 1250 1500 v v v cm = v + C 0.5v, npn mode l C1.6 C2.0 0.9 3.2 3.4 mv mv dv os input offset voltage match (channel-to-channel) (note 8) v cm = half supply l C350 C750 10 350 750 v v v cm = v + C 0.5v, npn mode l C2.8 C4 0.1 2.8 4 mv mv v os t c input offset voltage drift l 2.75 v/c i b input bias current (note 7) v cm = half supply l C1000 C1500 C275 600 900 na na v cm = v + C 0.5v, npn mode l 0.6 0 1.175 2.5 4.0 a a i os input offset current v cm = half supply l C500 C600 C150 500 600 na na v cm = v + C 0.5v, npn mode l C500 C600 C30 500 600 na na e n input noise voltage density f = 1mhz 2.9 nv/ hz input 1/f noise voltage f = 0.1hz to 10hz 2 v p-p i n input noise current density f = 1mhz 3.6 pa/ hz c in input capacitance differential mode common mode 2.5 0.8 pf pf r in input resistance differential mode common mode 7.2 3 k? m? a vol large signal voltage gain r l = 1k to half supply (note 12) l 16.5 7 36 v/mv v/mv r l = 100? to half supply (note 12) l 2.3 1.8 6.9 v/mv v/mv
LTC6252/ltc6253/ltc6254 6 625234fc electrical characteristics (v s = 2.7v) the l denotes the specifications which apply across the specified temperature range, otherwise specifications are at t a = 25c. for each amplifier v s = 2.7v, 0v; v shdn = 2v; v cm = v out = 1.35v, unless otherwise noted. symbol parameter conditions min typ max units cmrr common mode rejection ratio v cm = 0v to 1.2v l 80 77 105 db db v cmr input common mode range l 0 v s v psrr power supply rejection ratio v s = 2.5v to 5.25v v cm = 1v l 66.5 62 70 db db supply voltage range (note 6) l 2.5 5.25 v v ol output swing low (v out C v C ) no load l 22 28 40 mv mv i sink = 5ma l 80 100 140 mv mv i sink = 10ma l 110 150 190 mv mv v oh output swing high (v + C v out ) no load l 55 75 95 mv mv i source = 5ma l 125 150 200 mv mv i source = 10ma l 165 200 275 mv mv i sc short-circuit current sourcing l C35 C18 C14 ma ma sinking l 20 17 40 ma ma i s supply current per amplifier v cm = half supply l 2.9 3.5 4.5 ma ma v cm = v + C 0.5v l 3.7 4.6 5.5 ma ma i sd disable supply current v shdn = 0.8v l 24 35 50 a a i shdnl shdn pin current low v shdn = 0.8v l C1 C1.5 C0.5 0 0 a a i shdnh shdn pin current high v shdn = 2v l C300 C600 45 300 600 na na v l shdn pin input voltage l 0.8 v v h shdn pin input voltage l 2.0 v i osd output leakage current magnitude in shutdown v shdn = 0.8v, output shorted to either supply 100 na t on turn-on time v shdn = 0.8v to 2v 5 s t off turn-off time v shdn = 2v to 0.8v 2 s bw C3db closed loop bandwidth a v = 1, r l = 1k to half supply 350 mhz gbw gain-bandwidth product f = 4mhz, r l = 1k to half supply 630 mhz t s , 0.1 settling time to 0.1% a v = +1, v o = 2v step r l = 1k 34 ns sr slew rate a v = C1, 2v step (note 11) 170 v/s fpbw full power bandwidth v out = 2v p-p (note 13) 8.5 mhz crosstalk a v = C1, r l = 1k to half supply, v out = 2v p-p , f = 2.5mhz 96 db
LTC6252/ltc6253/ltc6254 7 625234fc electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the inputs are protected by back-to-back diodes. if any of the input or shutdown pins goes 300mv beyond either supply or the differential input voltage exceeds 1.4v the input current should be limited to less than 10ma. this parameter is guaranteed to meet specified performance through design and/or characterization. it is not production tested. note 3: a heat sink may be required to keep the junction temperature below the absolute maximum rating when the output current is high. this parameter is guaranteed to meet specified performance through design and/or characterization. it is not production tested. note 4: the LTC6252c/ltc6253c/ltc6254c and LTC6252i/ltc6253i/ ltc6254i are guaranteed functional over the temperature range of C40c to 85c. the LTC6252h/ltc6253h/ltc6254h are guaranteed functional over the temperature range of C40c to 125c. note 5: the LTC6252c/ltc6253c/ltc6254c are guaranteed to meet specified performance from 0c to 70c. the LTC6252c/ltc6253c/ ltc6254c are designed, characterized and expected to meet specified performance from C40c to 85c but are not tested or qa sampled at these temperatures. the LTC6252i/ltc6253i/ltc6254i are guaranteed to meet specified performance from C40c to 85c. the LTC6252h/ ltc6253h/ltc6254h are guaranteed to meet specified performance from C40c to 125c. note 6: supply voltage range is guaranteed by power supply rejection ratio test. note 7: the input bias current is the average of the average of the currents at the positive and negative input pins. note 8: matching parameters are the difference between amplifiers a and d and between b and c on the ltc6254; between the two amplifiers on the ltc6253. note 9: thermal resistance varies with the amount of pc board metal connected to the package. the specified values are with short traces connected to the leads with minimal metal area. note 10: the output voltage is varied from 0.5v to 4.5v during measurement. note 11: middle 2/3 of the output waveform is observed. r l = 1k to half supply. note 12: the output voltage is varied from 0.5v to 2.2v during measurement. note 13: fpbw is determined from distortion performance in a gain of +2 configuration with hd2, hd3 < C40dbc as the criteria for a valid output. note 14: differential gain and phase are measured using a tektronix tsg120yc/ntsc signal generator and a tektronix 1780r video measurement set. v os distribution, v cm = v s /2 (ms, pnp stage) v os distribution, v cm = v s /2 (tsot-23, pnp stage) v os distribution, v cm = v + C 0.5v (ms, npn stage) typical performance characteristics input offset voltage (v) percent of units (%) 40 30 20 5 0 35 25 15 10 625234 g01 250 150 50 ?50 ?150 ?250 v s = 5v, 0v v cm = 2.5v input offset voltage (v) percent of units (%) 40 15 5 20 25 35 30 10 0 ?150 ?50 625234 g02 150 50 250 ?250 v s = 5v, 0v v cm = 2.5v input offset voltage (v) percent of units (%) 16 12 8 2 14 10 6 4 0 ?1200 400 ?400 625234 g03 1200 2000 ?2000 v s = 5v, 0v v cm = 4.5v
LTC6252/ltc6253/ltc6254 8 625234fc typical performance characteristics offset voltage vs output current warm-up drift vs time input bias current vs common mode voltage offset voltage vs input common mode voltage v os vs temperature, v s = 2.7v, 0v (ms, pnp stage) v os distribution, v cm = v + C 0.5v (tsot-23, npn stage) v os vs temperature, v s = 2.7v, 0v (ms, npn stage) v os vs temperature, v s = 5v, 0v (ms, pnp stage) v os vs temperature, v s = 5v, 0v (ms, npn stage) input common mode voltage (v) 0 offset voltage (v) 600 400 ?200 0 ?1600 200 ?400 ?600 ?800 ?1200 ?1000 ?1400 ?1800 ?2000 1.5 3.5 1 2.5 4.5 625234 g09 5 3 0.5 2 4 ?55c v s = 5v, 0v 25c 125c output current (ma) ?100 offset voltage (mv) 3.0 1.5 0.5 ?1.0 1.0 2.5 2.0 0 ?0.5 ?1.5 ?2.0 ?2.5 ?3.0 ?75 25 ?25 75 625234 g10 100 0 ?50 50 ?55c 25c 125c v s = 2.5v time after power-up (sec) 0 change in offset voltage (v) 20 10 15 5 0 20 100 60 140 625234 g11 160 80 40 120 v s = 2.5v t a = 25c common mode voltage (v) 0 input bias current (na) 3000 2000 ?3000 1000 0 ?1000 ?2000 ?4000 ?5000 1.5 3.5 1 2.5 4.5 625234 g12 5 3 0.5 2 4 ?55c 25c 125c v s = 5v, 0v input offset voltage (v) percent of units (%) 18 12 14 10 4 16 8 6 2 0 ?1200 625234 g04 400 1200 ?400 2000 ?2000 v s = 5v, 0v v cm = 4.5v temperature (c) voltage offset (v) 300 0 100 ?100 ?400 200 ?200 ?300 ?500 ?600 ?15?35 625234 g05 5 25 65 85 105 125 ?55 v s = 5v, 0v v cm = 2.5v 6 devices 45 temperature (c) voltage offset (v) 2000 1000 1500 500 ?1000 0 ?500 ?1500 ?2000 ?2500 ?15?35 625234 g06 5 25 65 85 105 125 ?55 45 v s = 5v, 0v v cm = 4.5v 6 devices temperature (c) voltage offset (v) 1200 1000 1100 800 900 700 600 500 400 ?15?35 625234 g07 5 25 65 85 105 125 ?55 45 v s = 2.7v, 0v v cm = 1.35v 6 devices temperature (c) voltage offset (v) 3200 2200 2700 1700 1200 700 200 ?1300 ?800 ?300 ?1800 ?15?35 625234 g08 5 25 65 85 105 125 ?55 45 v s = 2.7v, 0v v cm = 2.2v 6 devices
LTC6252/ltc6253/ltc6254 9 625234fc typical performance characteristics supply current per amplifier vs shdn pin voltage shdn pin current vs shdn pin voltage input noise voltage and noise current vs frequency input bias current vs temperature supply current vs supply voltage (per amplifier) 0.1hz to 10hz voltage noise time (1s/div) 0 voltage noise (500nv/div) 2000 1500 1000 500 0 ?1000 ?500 ?1500 ?2000 1 7 3 9 624678 g14 10 4 5 6 2 8 total supply voltage (v) 0 supply current (ma) 5.0 4.5 4.0 3.5 3.0 1.5 1.0 2.5 2.0 0.5 0 1 3 625234 g16 4 5 2 ?55c 25c 125c temperature (c) ?55 input bias current (na) 3000 2000 0 2500 500 1500 1000 ?500 355?25 95 624678 g13 125 65 v s = 5v, 0v v cm = 4.5v v cm = 2.5v frequency (hz) 1 voltage noise (nv/ hz) current noise (pa/hz) 1000 100 10 1.0 0.1 10 1k 100m10m 624678 g15 10k 100k 1m 100 i n , v cm = 4.5v i n , v cm = 2.5v e n , v cm = 4.5v e n , v cm = 2.5v minimum supply voltage, v cm = v s /2 (pnp operation) minimum supply voltage, v cm = v + C 0.5v (npn operation) supply current vs input common mode voltage (per amplifier) common mode voltage (v) 0.25 1.25 supply current (ma) 5 4 3 2 3.25 625234 g17 4.25 4.75 2.25 125c 25c v s = 5v, 0v a v = 1 ?55c shdn pin voltage (v) 0 supply current (ma) 5.0 4.0 4.5 2.5 2.0 3.5 3.0 1.5 1.0 0.5 0 2.521.510.5 3.5 625234 g18 54 4.5 3 t a = 125c t a = 25c v s = 5v, 0v v cm = 2.5v t a = ?55c shdn pin voltage (v) 0 shdn pin current (a) 0.50 0.25 0 ?0.25 ?0.50 ?0.75 ?1.00 ?1.25 ?1.50 ?1.75 ?2.00 ?2.75 ?2.50 ?2.25 ?3.00 2.521.510.5 3.5 625234 g19 54 4.5 3 t a = 125c t a = 25c v s = 5v, 0v t a = ?55c total supply voltage (v) 2 offset voltage (mv) 16 10 12 14 8 6 4 2 0 ?2 2.5 3.5 625234 g20 5.5 125c 25c ?55c 4 4.5 5 3 v s = 5v, 0v total supply voltage (v) 2 offset voltage (mv) 16 10 12 14 8 6 4 2 0 ?4 ?2 2.5 3.5 625234 g21 5.5 125c ?55c 4 4.5 5 3 25c v s = 5v, 0v
LTC6252/ltc6253/ltc6254 10 625234fc typical performance characteristics open loop gain and phase vs frequency gain vs frequency (a v = 1) gain vs frequency (a v = 2) gain bandwidth and phase margin vs supply voltage open loop gain output short-circuit current vs supply voltage open loop gain output saturation voltage vs load current (output low) output saturation voltage vs load current (output high) load current (ma) output high saturation voltage (v) 625234 g22 10 1 0.1 0.01 0.01 10 100 1 0.1 t a = 125c t a = 25c v s = 2.5v t a = ?55c load current (ma) output high saturation voltage (v) 625234 g23 10 1 0.1 0.01 0.01 10 100 1 0.1 t a = 125c v s = 2.5v t a = ?55c t a = 25c total supply voltage (v) 1.25 output short-circuit current (ma) 160 120 80 40 0 ?40 ?80 ?120 ?160 1.751.5 625234 g24 2.5 2 2.25 t a = 125c t a = 125c t a = ?55c t a = ?55c t a = 25c t a = 25c sink source pulse tested output voltage (v) r l = 100 to mid supply v s = 5v, 0v t a = 25c r l = 1k to gnd r l = 1k to mid supply r l = 100 to gnd 0 input offset voltage (v) 500 400 300 200 100 0 ?100 ?200 ?300 ?400 ?500 2.5 3.5 625234 g25 54 4.5 21.510.5 3 output voltage (v) 0 input offset voltage (v) 1600 1400 600 800 1000 1200 400 200 0 ?200 ?400 ?600 2.5 625234 g26 21.510.5 r l = 1k to mid supply v s = 2.7v, 0v t a = 25c r l = 1k to gnd r l = 100 to mid supply r l = 100 to gnd frequency (mhz) gain (db) 625234 g27 2 0 ?8 ?6 ?2 ?4 ?10 0.01 10 100 1000 10.1 v s = 2.5v t a = 25c r l = 1k frequency (mhz) gain (db) 625234 g28 10 8 ?4 ?2 2 0 6 4 ?6 0.01 10 100 1000 10.1 v s = 2.5v t a = 25c r l = 1k r f = r g = 500 frequency (hz) gain (db) phase (deg) 625234 g29 75 5 15 25 35 45 55 65 ?5 120 30 45 60 75 90 105 15 0 300k 100m 1g 10m 1m gain t a = 25c r l = 1k phase v s = 2.5v v s = 1.35v v s = 2.5v v s = 1.35v total supply voltage (v) 2.5 gain bandwidth (mhz) phase margin (deg) 900 850 800 750 700 650 600 550 500 70 60 50 40 30 20 10 0 ?10 3 3.5 4.5 625234 g30 5 5.25 4 t a = 25c r l = 1k phase margin gain bandwidth product
LTC6252/ltc6253/ltc6254 11 625234fc typical performance characteristics power supply rejection ratio vs frequency series output resistor vs capacitive load (a v = 1) series output resistor vs capacitive load (a v = 2) output impedance vs frequency common mode rejection ratio vs frequency gain bandwidth and phase margin vs temperature slew rate vs temperature distortion vs frequency (a v = 1, 5v) distortion vs frequency (a v = 1, 2.7v) temperature (c) ?55 gain bandwidth (mhz) phase margin (deg) 900 1000 1100 1200 800 700 600 500 60 80 70 50 40 30 20 10 ?35 ?15 4525 625234 g31 125 65 85 105 5 v s = 2.5v v s = 1.35v v s = 2.5v v s = 1.35v phase margin gain bandwidth product t a = 25c r l = 1k frequency (mhz) output impedance () 625234 g32 1000 10 100 1 0.1 0.01 0.001 0.1 100 1000 10 1 v s = 2.5v a v = 1 a v = 2 a v = 10 frequency (hz) common mode rejection ratio (db) 625234 g33 110 90 70 50 30 10 ?10 10k 100k 1m 100m 1g 10m v s = 2.5v frequency (hz) 10 power supply rejection ratio (db) 50 40 30 20 10 70 80 60 0 ?10 100 1k 100k 625234 g34 1g100m10m1m 10k +psrr ?psrr v s = 2.5v temperature (c) ?55 slew rate (v/s) 360 320 340 300 280 240 260 220 200 140 120 160 180 100 ?30 45205 70 625234 g35 12095 a v = ?1, r l = 1k, v out = 4v p-p (2.5v), 2v p-p (1.35v) slew rate measured at middle 2/3 of output falling, v s = 2.5v rising, v s = 1.35v falling, v s = 1.35v rising, v s = 2.5v v s = 2.5v capacitive load (pf) 10 overshoot (%) 80 70 60 50 40 30 20 10 0 100 10000 1000 625234 g36 r s = 10 r s = 20 r s = 50 + ? v in r s v out c l v s = 2.5v capacitive load (pf) 10 overshoot (%) 100 70 80 90 60 50 40 30 20 10 0 100 10000 1000 625234 g37 + ? v in r s 500 500 v out c l r s = 10 r s = 20 r s = 50 v s = 2.5v frequency (mhz) 0.01 distortion (dbc) ?20 ?50 ?60 ?30 ?40 ?70 ?80 ?90 ?100 ?110 ?120 ?130 0.1 100 10 1 625234 g38 r l = 100, 2nd r l = 100, 3rd r l = 1k, 2nd r l = 1k, 3rd v s = 2.5v v out = 2v p-p a v = 1 frequency (mhz) 0.01 distortion (dbc) ?20 ?50 ?60 ?30 ?40 ?70 ?80 ?90 ?100 ?110 ?120 ?130 0.1 100 10 1 625234 g39 r l = 100, 2nd r l = 100, 3rd r l = 1k, 2nd r l = 1k, 3rd v s = 1.35v v out = 1v p-p a v = 1
LTC6252/ltc6253/ltc6254 12 625234fc typical performance characteristics large signal response small signal response output overdriven recovery 0.1% settling time vs output step (noninverting) 0.1% settling time vs output step (inverting) shdn pin response time distortion vs frequency a v = 2, 2.7v) maximum undistorted output signal vs frequency distortion vs frequency (a v = 2, 5v) frequency (mhz) 0.01 distortion (dbc) ?20 ?50 ?60 ?30 ?40 ?70 ?80 ?90 ?100 ?110 ?120 ?130 0.1 100 10 1 625234 g40 r l = 100, 2nd r l = 100, 3rd r l = 1k, 2nd r l = 1k, 3rd v s = 2.5v v out = 2v p-p a v = 2 frequency (mhz) 0.01 distortion (dbc) ?20 ?50 ?60 ?30 ?40 ?70 ?80 ?90 ?100 ?110 ?120 ?130 0.1 100 10 1 625234 g41 r l = 100, 2nd r l = 100, 3rd r l = 1k, 2nd r l = 1k, 3rd v s = 1.35v v out = 1v p-p a v = 2 frequency (mhz) 0.01 output voltage swing (v p-p ) 6 4 5 3 2 1 0 0.1 100 10 1 625234 g42 v s = 2.5v t a = 25c r l = 1k hd2, hd3 < ?40dbc a v = 2 a v = ?1 output step (v) ?4 settling time (ns) 50 45 40 35 10 15 20 25 30 5 0 ?3 ?1 625234 g43 4 0 1 32 ?2 v s = 2.5v a v = 1 t a = 25c + ? v out 1k v in output step (v) ?4 settling time (ns) 60 45 40 55 50 35 10 15 20 25 30 5 0 ?3 ?1 625234 g44 4 0 1 32 ?2 v s = 2.5v a v = ?1 t a = 25c + ? v out 1k 500 v in 500 v out 0.8v/div a v = 1 v s = 2.5v r l = 1k v in = 1.6v v shdn 2.5v/div 0v 0v 625234 g45 2s/div 1v/div 0v a v = 1 v s = 2.5v t a = 25c r l = 1k 625234 g46 100ns/div input (50mv/div) 0v output (50mv/div) 0v v s = 2.5v r l = 1k 625234 g47 20ns/div v out 2v/div a v = 2, t a = 25c v s = 2.5v, v in = 3v p-p r l = 1k, r f = r g = 500 v in 1v/div 0v 0v 625234 g48 20ns/div
LTC6252/ltc6253/ltc6254 13 625234fc applications information circuit description the LTC6252/ltc6253/ltc6254 have an input and output signal range that extends from the negative power supply to the positive power supply. figure 1 depicts a simplified schematic of the amplifier. the input stage is comprised of two differential amplifiers, a pnp stage, q1/q2, and an npn stage, q3/q4 that are active over different common mode input voltages. the pnp stage is active between the negative supply to nominally 1.2v below the positive supply. as the input voltage approaches the positive sup - ply, the transistor q5 will steer the tail current, i 1 , to the current mirror, q6/q7, activating the npn differential pair and the pnp pair becomes inactive for the remaining input common mode range. also, at the input stage, devices q17 to q19 act to cancel the bias current of the pnp input pair. when q1/q2 are active, the current in q16 is controlled to be the same as the current in q1 and q2. thus, the base current of q16 is nominally equal to the base current of the input devices. the base current of q16 is then mirrored by devices q17 to q19 to cancel the base current of the input devices q1/q2. a pair of complementary common emitter stages, q14/q15, enable the output to swing from rail-to-rail. figure 1. LTC6252/ltc6253/ltc6254 simplified schematic diagram Cin: inverting input of amplifier. input range from v C to v + . +in: non-inverting input of amplifier. input range from v C to v + . v + : positive supply voltage. total supply voltage ranges from 2.5v to 5.25v. v C : negative supply voltage. typically 0v. this can be made a negative voltage as long as 2.5v (v + C v C ) 5.25v. shdn: active low shutdown. threshold is typically 1.1v referenced to v C . floating this pin will turn the part on. out: amplifier output. swings rail-to-rail and can typically source/sink over 90ma of current at a total supply of 5v. pin functions 625234 f01 q15 esdd5 q14 c2 c1 buffer and output bias r5 r4 q13 q12 i 3 v ? + c c q8 r3 q11 q9 q10 r2 r1 q2q1 q3q4 i 1 + i 2 + v bias q5 q6 q19 q7 d8 d7 q18 q17 d6 d5 esdd2 v ? esdd1 v + esdd4 v ? esdd3 v + q16 v ? v + +in ?in esdd6 out
LTC6252/ltc6253/ltc6254 14 625234fc applications information input offset voltage the offset voltage will change depending upon which input stage is active. the pnp input stage is active from the negative supply rail to approximately 1.2v below the positive supply rail, then the npn input stage is activated for the remaining input range up to the positive supply rail with the pnp stage inactive. the offset voltage magnitude for the pnp input stage is trimmed to less than 350v with 5v total supply at room temperature, and is typically less than 150v. the offset voltage for the npn input stage is less than 2.2mv with 5v total supply at room temperature. input bias current the LTC6252 family uses a bias current cancellation cir - cuit to compensate for the base current of the pnp input pair. this results in a typical i b of about 100na. when the input common mode voltage is less than 200mv, the bias cancellation circuit is no longer effective and the input bias current magnitude can reach a value above 4a. for common mode voltages ranging from 0.2v above the negative supply to 1.2v below the positive supply, the low input bias current allows the amplifiers to be used in applications with high source resistances where errors due to voltage drops must be minimized. output the LTC6252 family has excellent output drive capability. the amplifiers can typically deliver 90ma of output drive current at a total supply of 5v. the maximum output current is a function of the total supply voltage. as the supply voltage to the amplifier decreases, the output current capability also decreases. attention must be paid to keep the junction temperature of the ic below 150c (refer to the power dissipation section) when the output is in continuous short-circuit. the output of the amplifier has reverse-biased diodes connected to each supply. if the output is forced beyond either supply, extremely high current will flow through these diodes which can result in damage to the device. forcing the output to even 1v beyond either supply could result in several hundred mil - liamps of current through either diode. input protection the LTC6252/ltc6253/ltc6254 input stages are protected against a large differential input voltage of 1.4v or higher by 2 pairs of back-to-back diodes to prevent the emitter- base breakdown of the input transistors. in addition, the input and shutdown pins have reverse biased diodes con - nected to the supplies. the current in these diodes must be limited to less than 10ma. the amplifiers should not be used as comparators or in other open loop applications. esd the LTC6252 family has reverse-biased esd protection diodes on all inputs and outputs as shown in figure 1. there is an additional clamp between the positive and negative supplies that further protects the device during esd strikes. hot plugging of the device into a powered socket must be avoided since this can trigger the clamp resulting in larger currents flowing between the supply pins. capacitive loads the LTC6252/ltc6253/ltc6254 are optimized for high bandwidth and low power applications. consequently they have not been designed to directly drive large capacitive loads. increased capacitance at the output creates an ad - ditional pole in the open loop frequency response, wors - ening the phase margin. when driving capacitive loads, a resistor of 10 to 100 should be connected between the amplifier output and the capacitive load to avoid ringing or oscillation. the feedback should be taken directly from the amplifier output. higher voltage gain configurations tend to have better capacitive drive capability than lower gain configurations due to lower closed loop bandwidth and hence higher phase margin. the graphs titled series output resistor vs capacitive load demonstrate the tran - sient response of the amplifier when driving capacitive loads with various series resistors.
LTC6252/ltc6253/ltc6254 15 625234fc applications information figure 2. 5pf feedback cancels parasitic pole feedback components when feedback resistors are used to set up gain, care must be taken to ensure that the pole formed by the feedback resistors and the parasitic capacitance at the inverting input does not degrade stability. for example if the amplifier is set up in a gain of +2 configuration with gain and feedback resistors of 5k, a parasitic ca- pacitance of 5pf (device + pc board) at the amplifiers inverting input will cause the part to oscillate, due to a pole formed at 12.7mhz. an additional capacitor of 5pf across the feedback resistor as shown in figure 2 will eliminate any ringing or oscillation. in general, if the resistive feedback network results in a pole whose frequency lies within the closed loop bandwidth of the amplifier, a capacitor can be added in parallel with the feedback resistor to introduce a zero whose frequency is close to the frequency of the pole, improving stability. 624678 f02 c par 5k ? + v out v in 5k 5pf power dissipation the LTC6252 and ltc6253 contain one and two amplifiers respectively. hence the maximum on-chip power dissipa - tion for them will be less than the maximum on-chip power dissipation for the ltc6254, which contains four amplifiers. the ltc6254 is housed in a small 16-lead ms package and typically has a thermal resistance (q ja ) of 125c/ w. it is necessary to ensure that the dies junction temperature does not exceed 150c. the junction temperature, t j , is calculated from the ambient temperature, t a , power dis- sipation, pd, and thermal resistance, q ja : t j = t a + (p d ? q ja ) the power dissipation in the ic is a function of the supply voltage, output voltage and load resistance. for a given supply voltage with output connected to ground or supply, the worst-case power dissipation p d(max) occurs when the supply current is maximum and the output voltage at half of either supply voltage for a given load resistance. p d(max) is approximately (since i s actually changes with output load current) given by: p d(max) = (v s ? i s(max) ) + v s 2 ? ? ? ? ? ? 2 / r l example: for an ltc6254 in a 16-lead ms package operating on 2.5v supplies and driving a 100 load to ground, the worst-case power dissipation is approximately given by p d(max) /amp = (5 ? 4.8ma) + (1.25) 2 /100 = 39.6mw if all four amplifiers are loaded simultaneously then the total power dissipation is 158mw. at the absolute maximum ambient operating temperature, the junction temperature under these conditions will be: t j = t a + p d ? 125c/w = 125 + (0.158w ? 125c/w) = 145c which is less than the absolute maximum junction tem - perature for the ltc6254 (150c). refer to the pin configuration section for thermal resis - tances of various packages. shutdown the LTC6252 and ltc6253ms have shdn pins that can shut down the amplifier to 42a typical supply current. the shdn pin needs to be taken within 0.8v of the negative supply for the amplifier to shut down. when left floating, the shdn pin is internally pulled up to the positive supply and the amplifier remains on.
LTC6252/ltc6253/ltc6254 16 625234fc figure 3. 5v single supply 16-bit adc driver typical applications 5v single-supply 16-bit adc driver figure 3 shows the ltc6253 driving an ltc2393-16 16-bit a/d converter on a single 5v supply. the low wideband noise of the ltc6253 helps to achieve better than 93db snr. a gain of 1.17v/v is taken in the first amplifier, giv - ing an input voltage range of 3.5v p-p for a full-scale input to the adc. by taking a small amount of gain, a C1dbfs figure 4. ltc6253 driving ltc2393-16 16b adc 5v single-supply performance 5v 0.1f 10f 5v 5v ~2.08v 0.1f 10f ser/ par byteswap ob/2c cs rd busy parallel or serial interface ognd 625234 f03 in ? in + 3900pf 249 249 100 100 v in 27.4mv to (3.5v + 27.4mv) gnd reset cnvst pd sample clock refout refin avp dvp ltc2393-16 ovp 1.8v to 5v 16 bit vcm 1f 10f 2.5k 2.5k 143 845 4.7f ? + ? ltc6253 5v ? + ? ltc6253 frequency (khz) 0 amplitude (dbfs) 0 ?80 ?20 ?40 ?60 ?100 ?120 ?140 ?160 200 400 100 300 624678 f04 500 f s = 1msps f1 = 20.111khz f1 amplitude = ?1.032dbfs snr = 93.28db thd = ?100.50db sinad = 92.53db sfdr = 104.7db f2 = ?106.39dbc f3 = ?104.70dbc f4 = ?114.13dbc f5 = ?105.48dbc output can be easily obtained without the amplifier transi - tioning between input regions, thus minimizing crossover distortion. furthermore, by driving vcm with 2.08v from the adcs vcm pin, the ltc6253 is capable of driving the ltc2393-16 to within 0.1db of full scale. figure 4 shows an fft obtained with a sampling rate of 1msps and a 20khz input waveform. spurious free dynamic range is an excellent 104.7db.
LTC6252/ltc6253/ltc6254 17 625234fc low noise gain block using channels in parallel figure 5 shows the ltc6254 configured as a low noise gain block. by configuring each channel as a gain of 10 block and putting all four gain blocks in parallel, the input referred noise can be reduced significantly. 22 resistors are hooked up to the outputs of each of the channels to ensure even distribution of load currents.for a total sup - ply current of 13.2ma, measured input referred noise density (including contributions from the resistors) be - tween 100khz and 10mhz was less than 1.6nv/ hz, with input referred noise density at 1 mhz being 1.5nv/ hz. the measured C3db frequency was 37mhz for a load resistance of 1k. typical applications multiplexing channels the LTC6252 and ltc6253 are available with shutdown pins in the sot-23 and ms10 packages. while this allows for reduced power consumption, it also makes the parts suitable for high output impedance applications such as muxing. during shutdown, the bases of the amplifiers output channels are hard tied to their emitters in order to minimize leakage. figure 6 shows the ltc6253 applied as a mux, with the outputs simply shorted together. depending on which device is powered, either the v a or the v b input is buffered to v out . the mosfet q1 provides a simple logic inversion, so that pulling the gate high selects the b path while the fet drain goes low shutting down the a path. r3 is provided to speed up the drain rise time. the ltc6253 turn-on time is longer than the turn-off time (3.5s vs < 2s) avoiding cross conduction in the output figure 5. low noise gain block using parallel channels figure 6. multiplexing channels ? ltc6254 + ? 1pf 2.5v ?2.5v 900 100 22 ? ltc6254 + ? 1pf 900 100 22 ? ltc6254 + ? 1pf 900 100 22 ? ltc6254 + ? 1pf 900 100 v in 22 v out 625234 f05 625234 f06 + ? 5v shdna shdnb v a ? ltc6253 r1 330 + ? v b 5v q1 2n7002 sel_b ? ltc6253 r2 330 r3 20k v out
LTC6252/ltc6253/ltc6254 18 625234fc typical applications figure 9. instrumentation amplifier frequency response frequency (hz) 10k gain (db) 40 35 25 15 30 20 10 5 0 100k 10m 1m 625234 f09 100m frequency (hz) 10k cmrr (db) 120 100 60 20 80 40 0 100k 10m 1m 625234 f10 100m figure 10. instrumentation amplifier cmrr input 25mv/div output 1v/div 0v 0v 625234 f11 100ns/div figure 11. transient response, instrumentation amplifier figure 8. high speed low voltage instrumentation amplifier 625234 f08 + ? r4 750 r5 750 r6 750 r7 750 r2 1.2k r1 60 u1 ? ltc6253 v s + v s ? r3 1.2k a v = 41 bw = 15mhz v s = 1.5v i s = 8.4ma ? + u2 ? ltc6253 in + in ? v s + v s ? + ? u3 ? ltc6253 v out stages. see the oscillograph of figure 7, showing the inputs v a and v b , the sel_b control, and the resulting output. note that there are protection diodes across the op amp inputs, so large signals at the output will feed back into the upstream off channel through the diodes. r1 and r2 were put in place to reduce the loading on the output, as well as to reduce the upstream feedback current and improve reverse isolation. some reverse crosstalk can be discerned in the v a and v b traces during their respective off times, however, as the reverse current works back into the 50 source impedance of the function generators. high speed low voltage instrumentation amplifier figure 8 shows a three op amp instrumentation amplifier with a gain of 41v/v which can operate on low supplies. op amps u1 and u2 are channels from an ltc6253. op amp u3 can be an LTC6252 or one channel of an ltc6253. figure 9 shows the measured frequency re - sponse of the instrumentation amplifier for a load of 1k. figure 10 shows the measured cmrr of the instrumenta - tion amplifier, and figure 11 shows the transient response for a 50mv p-p input square wave applied to the positive input, with the negative input grounded. figure 7. oscilloscope traces showing multiplexing channels sel_b 5v/div v b v a v out 625234 f07 50s/div
LTC6252/ltc6253/ltc6254 19 625234fc package description 2.00 0.10 (4 sides) note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 0.64 0.10 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.05 typ 1.37 0.10 (2 sides) 1 4 8 5 pin 1 bar top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dc8) dfn 0106 rev? 0.23 0.05 0.45 bsc 0.25 0.05 1.37 0.05 (2 sides) recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.64 0.05 (2 sides) 1.15 0.05 0.70 0.05 2.55 0.05 package outline 0.45 bsc pin 1 notch r = 0.20 or 0.25 45 chamfer dc8 package 8-lead plastic dfn (2mm 2mm) (reference ltc dwg # 05-08-1719 rev a) please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LTC6252/ltc6253/ltc6254 20 625234fc package description ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660 rev f) msop (ms8) 0307 rev f 0.53 0.152 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 ? 0.38 (.009 ? .015) typ 0.1016 0.0508 (.004 .002) 0.86 (.034) ref 0.65 (.0256) bsc 0 ? 6 typ detail ?a? detail ?a? gauge plane 1 2 3 4 4.90 0.152 (.193 .006) 8 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) 0.52 (.0205) ref 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LTC6252/ltc6253/ltc6254 21 625234fc package description ms package 10-lead plastic msop (reference ltc dwg # 05-08-1661 rev e) msop (ms) 0307 rev e 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ? 0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 12 3 45 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8910 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc 0.1016 0.0508 (.004 .002) please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LTC6252/ltc6253/ltc6254 22 625234fc package description ms package 16-lead plastic msop (reference ltc dwg # 05-08-1669 rev ?) msop (ms16) 1107 rev ? 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16151413121110 1 2 3 4 5 6 7 8 9 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc 4.039 0.102 (.159 .004) (note 3) 0.1016 0.0508 (.004 .002) 3.00 0.102 (.118 .004) (note 4) 0.280 0.076 (.011 .003) ref 4.90 0.152 (.193 .006) ms package 16-lead plastic msop (reference ltc dwg # 05-08-1669 rev ?) please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LTC6252/ltc6253/ltc6254 23 625234fc s6 package 6-lead plastic tsot-23 (reference ltc dwg # 05-08-1636) package description 1.50 ? 1.75 (note 4) 2.80 bsc 0.30 ? 0.45 6 plcs (note 3) datum ?a? 0.09 ? 0.20 (note 3) s6 tsot-23 0302 rev b 2.90 bsc (note 4) 0.95 bsc 1.90 bsc 0.80 ? 0.90 1.00 max 0.01 ? 0.10 0.20 bsc 0.30 ? 0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.62 max 0.95 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LTC6252/ltc6253/ltc6254 24 625234fc package description 1.50 ? 1.75 (note 4) 2.80 bsc 0.22 ? 0.36 8 plcs (note 3) datum ?a? 0.09 ? 0.20 (note 3) ts8 tsot-23 0710 rev a 2.90 bsc (note 4) 0.65 bsc 1.95 bsc 0.80 ? 0.90 1.00 max 0.01 ? 0.10 0.20 bsc 0.30 ? 0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.40 max 0.65 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref ts8 package 8-lead plastic tsot-23 (reference ltc dwg # 05-08-1637 rev a) please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LTC6252/ltc6253/ltc6254 25 625234fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 9/10 revised i sd parameters in electrical characteristics section 4, 5 b 6/11 added h-grade ms8 to order information section 2 c 1/12 updated electrical characteristics 3 to 6
LTC6252/ltc6253/ltc6254 26 625234fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2010 lt 0112 rev c ? printed in usa typical application part number description comments operational amplifiers lt1818/lt1819 single/dual wide bandwidth, high slew rate low noise and distortion op amps 400mhz, 9ma, 6nv/ hz , 2500v/s, 1.5mv C85dbc at 5mhz lt1806/lt1807 single/dual low noise rail-to-rail input and output op amps 325mhz, 13ma, 3.5nv/ hz , 140v/s, 550v, 85ma output drive ltc6246/ltc6247/ ltc6248 single/dual/quad high speed rail-to-rail input and output op amps 180mhz, 1ma, 4.2nv/ hz , 90v/s, 0.5mv lt6230/lt6231/ lt6232 single/dual/quad low noise rail-to-rail output op amps 215mhz, 3.5ma, 1.1nv/ hz , 70v/s, 350v lt6200/lt6201 single/dual ultralow noise rail-to-rail input/output op amps 165mhz, 20ma, 0.95nv/ hz , 44v/s, 1mv lt6202/lt6203/ lt6204 single/dual/quad ultralow noise rail-to-rail op amp 100mhz, 3ma, 1.9nv/ hz , 25v/s, 0.5mv lt1468 16-bit accurate precision high speed op amp 90mhz, 3.9ma, 5nv/ hz , 22v/s, 175v, C96.5db thd at 10v p-p , 100khz lt1801/lt1802 dual/quad low power high speed rail-to-rail input and output op amps 80mhz, 2ma, 8.5nvhz , 25v/s, 350v lt1028 ultralow noise, precision high speed op amps 75mhz, 9.5ma, 0.85nv/ hz , 11v/s, 40v ltc6350 low noise single-ended to differential converter/adc driver 33mhz (C3db), 4.8ma, 1.9nv/ hz , 240ns settling to 0.01% 8v p-p adcs ltc2393-16 1msps 16-bit sar adc 94db snr ltc2366 3msps, 12-bit adc serial i/o 72db snr, 7.8mw no data latency tsot-23 package ltc2365 1msps, 12-bit adc serial i/o 73db snr, 7.8mw no data latency tsot-23 package related parts 2mhz, 1m single supply photodiode amplifier photodiode amplifier noise spectrum photodiode amplifier transient response LTC6252 + ? 625234 ta02a v out 0.5v + i pd ? 1m 3v r1 1m, 1% 3v 3v r2 1k i pd c3 0.1f c1 0.1pf r5 20k r4 10k r3 1k C3db bw = 2mhz i cc = 4.5ma output noise = 360v rms measured on a 2mhz bw c2 6.8nf film or npo pd1 osram sfh213 q1 nxp bf862 50nv/ hz per div 500 0 625234 ta02b 100khz 2mhz 5khz 0v 5v/div led driver voltage 625234 ta02c 200ns/div 500mv/div output waveform

▲Up To Search▲

Price & Availability of LTC6252

	To Download LTC6252 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .